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MPC235 Low-Speed USB Micro-Controller
General Description........................................................................................................................................ 3 Features .......................................................................................................................................................... 4 Pin Description ............................................................................................................................................... 5 Block Diagram ............................................................................................................................................... 6 Packages ......................................................................................................................................................... 7 Function Description ...................................................................................................................................... 8 Memory Map.................................................................................................................................................. 9 Special Function Register (SFR) .................................................................................................................. 10 Interrupt Vectors ............................................................................................................................................11 Interrupt Registers ................................................................................................................................ 12 IRQ enable flag............................................................................................................................. 12 IRQ status flag.............................................................................................................................. 12 IRQ clear flag ............................................................................................................................... 12 Watchdog Timer (WDT)............................................................................................................................... 13 System Control Registers ............................................................................................................................. 14 Power saving control ............................................................................................................................ 14 Release halt mode enable flag .............................................................................................................. 14 FCPU selector............................................................................................................................................... 15 Timer ............................................................................................................................................................ 16 Timer 0 ................................................................................................................................................. 16 USB .............................................................................................................................................................. 17 USB Block Diagram............................................................................................................................. 17 USB register access control.................................................................................................................. 17 USB SFR Category - Descriptions Summary....................................................................................... 18 USB SFR Description........................................................................................................................... 19 DCON: Device Control Register .................................................................................................. 19 FADDR: USB Function Address Register.................................................................................... 19 FPCON: Function Power Control Register .................................................................................. 20 FIE: Function Interrupt Enable Register....................................................................................... 20 FIFLG: Function Interrupt Flag Register...................................................................................... 21 IEN1: USB Interrupt Enable Register .......................................................................................... 21 EPINDEX: Endpoint Index Register ............................................................................................ 22 EPCON: Endpoint Control Register (Endpoint-Indexed)............................................................. 22 RXCNT: Receive FIFO Byte-Count Register (Endpoint-Indexed) .............................................. 23 RXCON: Receive FIFO Control Register (Endpoint-Indexed) .................................................... 23 RXDAT: Receive FIFO Data Register (Endpoint-Indexed) ......................................................... 24 RXSTAT: Endpoint Receive Status Register (Endpoint-Indexed)................................................ 24 TXCNT: Transmit FIFO Byte-Count Register (Endpoint-Indexed) ............................................. 25 TXCON: Transmit FIFO Control Register (Endpoint-Indexed)................................................... 25 TXDAT: Transmit FIFO Data Register (Endpoint-Indexed) ........................................................ 26 TXSTAT: Endpoint Transmit Status Register (Endpoint-Indexed)............................................... 26 I/O Ports ....................................................................................................................................................... 27 Port 0 .................................................................................................................................................... 27 Port 1 .................................................................................................................................................... 27 Port 2 .................................................................................................................................................... 28 Port 3 .................................................................................................................................................... 28 Port 4 .................................................................................................................................................... 28 DPM control ......................................................................................................................................... 29 Programming Notice .................................................................................................................................... 30 Application Circuit ....................................................................................................................................... 31 Normal:................................................................................................................................................. 31
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. (c) Megawin Technology Co., Ltd. 2008 All rights reserved. 2008/12 version A4
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USB keyboard: ..................................................................................................................................... 31 Pad Assignment ............................................................................................................................................ 32 MPC235................................................................................................................................................ 32 Absolute Maximum Rating .......................................................................................................................... 34 DC Characteristics........................................................................................................................................ 35 AC Characteristics........................................................................................................................................ 36 Instruction Set Summary .............................................................................................................................. 37 Addressing Mode Table........................................................................................................................ 37 Instruction Set Table ............................................................................................................................. 38 Instruction Set Summary ...................................................................................................................... 39 Symbol Description .............................................................................................................................. 41 Arithmetic Operations .......................................................................................................................... 42 Logic Operations .................................................................................................................................. 44 Data Transfer ........................................................................................................................................ 46 Boolean Variable Manipulation ............................................................................................................ 47 Program and Machine Control ............................................................................................................. 48 Package Dimensions..................................................................................................................................... 49 40-pin DIP ............................................................................................................................................ 49 28-SSOP ............................................................................................................................................... 49 Version History............................................................................................................................................. 50
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MPC235 Data Sheet
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General Description
The MPC235 is a 65C02 MCU with an embedded 8K bytes ROM, a 256 bytes RAM, a watch-dog timer, a USB and PS/2 combo interfaces, can be implemented via the USB bus line, D+ and Dpins, by the user's program. The USB features fully meet the low-speed USB Specification version 1.1. It will be very suitable for the low-cost keyboard, joystick, I-toy, and some products like the hand-held devices, which need to download/ upload data through the PC system.
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MPC235 Data Sheet
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Features
The MPC235 is mask version of the MPC2F35 8-bit 65C02 micro-controller with 6MHz external crystal or ceramic resonator Memory: - 8K Bytes ROM - 256 Bytes RAM 34 programmable GPIO: - 4 LED direct sink pins shared with Port0 (LED0/1/2/3) - 2 external interrupt pins (-INT0, -INT1) - Port3 provides the pin interrupt - 34 bi-directional I/O pins for Port0/1/ 2/3/4 One 8-bit programmable timer Built-in power-on reset One watchdog timer Low-speed USB Specification version 1.1 compliance. - Supports 4 endpoints, where EP0 is control endpoint, and EP1/2/3 are data endpoints. - Integrated USB transceiver and USB built-in pull-up resistor. - Provides remote-wake-up/host-resume from suspend mode. - Built-in 5V to 3.3V regulator for USB. Built-in low-voltage detector (reset) USB and PS/2 combo interfaces Support suspend/normal mode for power management Operating voltage: 4.35V to 5.5V Operating temperature: 0C to 70C Packages: - 28-SSOP: MPC235L - 40-PDIP: MPC235E2
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MPC235 Data Sheet
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Pin Description
Description Bi-directional I/O (sink LED directly) Bi-directional I/O with external interrupt 1 Bi-directional I/O with external interrupt 2 Bi-directional I/O Bi-directional I/O Bi-directional I/O Bi-directional I/O Bi-directional I/O Reset pin 6MHz crystal or resonator in 6MHz crystal or resonator out USB data + with PS/2 compatible I/O USB data - with PS/2 compatible I/O Voltage supply Ground 3.3V regulated output, a 0.1uF to 1uF capacitor should be V3.3 O added on this pin *1 P0.0~0.3 can be used to sink LED directly (without any external resistor). *2 P4.0~P4.1 only available on Die form. PIN Name P0.0~0.3 *1 P0.4/-INT0 P0.5/-INT1 P0.6~0.7 P1.0~1.7 P2.0~2.7 P3.0~3.7 P4.0~4.1 *2 RESB XTAL1 XTAL2 DP DM VCC VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O I/O I/O I I
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MPC235 Data Sheet
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Block Diagram
W65C02 8-bits CPU DP / PS2CLK DM / PS2DATA
256 Bytes RAM 8K Bytes ROM 8-bits Timer Power Control Low-voltage Reset Watch Dog Timer
DPM Control USB Control Clock Generator Port 0/1/2/4 Configurable I/O
XTAL1 XTAL2 Port 0.0 ~ 0.7 Port 1.0 ~ 1.7 Port 2.0 ~ 2.7 Port 4.0 ~ 4.1 Port 3.0 ~ 3.7
Port 3 Configurable I/O Interrupt Control
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MPC235 Data Sheet
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Packages
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MPC235 Data Sheet
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Function Description
Registers A Y X P PCL S
PCH 1
Accumulator The accumulator is a general-purpose 8-bit register, which stores the results of most arithmetic and logic operations. In addition, the accumulator usually contains one of two data words used in these operations. Index Register (X, Y) There are two 8-bit index registers (X and Y), which may be used to count program steps or to provide an index value to be used in generating an effective address. When executing an instruction, which specifies indexed addressing, the CPU fetches the OP Code and the base address, and modifies the address by adding the index register to it prior to performing the desired operation. Pre- or post-index of index address is possible. Processor Status Register (P) The 8-bit processor status register contains seven status flags. Some of the flags are controlled by the program, others may be controlled both the program and the CPU. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N V 1 B D I Z C N: Signed flag, 1 = negative, 0 = positive V: Overflow flag, 1 = true, 0 = false B: BRK interrupt command, 1 = BRK, 0 = IRQB D: Decimal mode, 1 = true, 0 = false I: IRQB disable flag, 1 = disable, 0 = enable Z: Zero flag, 1 = true, 0 = false C: Carry flag, 1 = true, 0 = false Program Counter (PC) The 16-bit program counter register provides the addresses, which step the micro-controller through sequential program instructions. Each time the micro-controller fetch an instruction from program memory, the lower byte of the program counter (PCL) is placed on the low-order 8 bits of the address bus and the higher byte of the program counter (PCH) is placed on the high-order 8 bits. The counter is incremented each time an instruction or data is fetched from program memory. Stack Pointer (S) The stack pointer is an 8-bit register, which is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under control of the micro-controller to perform stack manipulations under direction of either the program or interrupts (/NMI or /IRQ). The stack allows simple implementation of nested subroutines and multiple level interrupts. The stack pointer is initialized by the user's firmware.
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MPC235 Data Sheet
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Memory Map
There are 256 bytes SRAM in MPC235. They are working RAM (0000H to 007FH) and stacks (0180H to 01FFH). Locations 0100h to 017FH and the locations 0000h to 007FH share the same memory block. The address 00C0H to 00FFH and 0200H to 027FH are special function registers area. The 8k bytes ROM are addressed from 8000H to 9FFFH. The address mapping of MPC235 series is shown as below.
0000H ~ 007FH 0080H ~ 00BFH 00C0H ~ 00FFH 0100H ~ 017FH
Zero Page SRAM
Share Area SFR -
0180H ~ 01FFH
Stack Area
0200H ~ 027FH 0280H
Special Function Register
7FFFH 8000H ~ 800FH Interrupt Vector Area
8010H ~ 9FFFH
Program / Table
A000H
FFFFH
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MPC235 Data Sheet
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Special Function Register (SFR)
The address 00C0H to 00FFH and 0200H to 027FH are reserved for special function registers (SFR). The SFR is used to control or store the status of I/O, timers, system clock and other peripheral. Symbol IRQ_EN IRQ_ST IRQ_CLR TM0 TM0_CTL P0_BUF P1_BUF P2_BUF P3_BUF P4_BUF P0 P1 P2 P3 P4 WDT_ST WDT_CLR USB_CTL USB_ADDR USB_DI / USB_DO DPM_CTL DPMO DPMI PWR_CTL FCPU_SR RLH_EN P0_CR P0_MR P1_CR P1_MR P2_CR P2_MR P3_CR P3_MR P4_CR P4_MR Address 00C1 00C2 00C3 00C5 00C6 00D0 00D1 00D2 00D3 00D4 00D8 00D9 00DA 00DB 00DC 00DE 00DF 00E0 00E1 00E2 00E8 00E9 00EA 0200 0201 0202 0240 0241 0244 0245 0248 0249 024C 024D 0250 0251 Description Interrupt Request Enable Interrupt Request Status Flag Interrupt Request Clear Timer 0 Timer 0 Control Port 0 Output Buffer Port 1 Output Buffer Port 2 Output Buffer Port 3 Output Buffer Port 4 Output Buffer Port 0 Pad Value Port 1 Pad Value Port 2 Pad Value Port 3 Pad Value Port 4 Pad Value Watch Dog Timer Status Flag Watch Dog Timer Status Clear USB Control USB Register Address USB Register Data Buffer USB Bus Mode Control USB Bus Output for the PS/2 Mode USB Bus Output for the PS/2 Mode Power-Saving Control FCPU Selector Release Halt Mode Enable Port 0 Control Register Port 0 Mode Register Port 1 Control Register Port 1 Mode Register Port 2 Control Register Port 2 Mode Register Port 3 Control Register Port 3 Mode Register Port 4 Control Register Port 4 Mode Register Initial Value X 00 00 00 00 00 00 00 00 00 X X X X X 00 X 00 00 00 00 00 X 00 00 00 00 00 00 00 00 00 00 00 00 00
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MPC235 Data Sheet
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Interrupt Vectors
Vector Address 8002H, 8003H 8006H, 8007H 8008H, 8009H 800AH, 800BH 800CH, 800DH 800EH, 800FH Item RESET USB TM0 P3 P04 P05 Priority 1 2 3 4 5 6 Properties Ext. Int. Int. Ext. Ext. Ext. Memo Initial reset USB interrupt Timer 0 overflow interrupt Port P3 interrupt vector Port P0.4 interrupt vector Port P0.5 interrupt vector
There are six interrupt sources provided in MPC235. The flag IRQ_EN and IRQ_ST are used to control the interrupts. When flag IRQ_ST is set to `1' by hardware and the corresponding bits of flag IRQ_EN has been set by firmware, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the CLI or STA IRQ_CLR, #I instruction is invoked. Executing the SEI instruction can also disable the interrupts.
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MPC235 Data Sheet
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Interrupt Registers
IRQ enable flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 00C1H IRQ_EN P05 P04 P3 TM0 USB Program can enable or disable the ability of triggering IRQ through this register. 0: Disable (default "0" at initialization) 1: Enable USB: USB event TM0: Timer0 underflow P3: Falling edge occurs at port 3 input mode P04, P05: Falling edge occurs at P0.4/P0.5 input mode Bit 0 R W
IRQ status flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00C2H IRQ_ST P05 P04 P3 TM0 USB When IRQ occurs, program can read this register to know which source triggering IRQ.
R
W -
IRQ clear flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 00C3H IRQ_CLR P05 P04 P3 TM0 USB Program can clear the interrupt event by writing `1' into the corresponding bit.
Bit 0 -
R -
W
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MPC235 Data Sheet
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Watchdog Timer (WDT)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W WDT 3 WDT 2 WDT 1 WDT 0 RSTS 00DEH WDT_ST 00DFH WDT_CLR CLR - WDT3:0 : Contents of WDT RSTS: WDT reset status, set by hardware when WDT overflows, clear by firmware or hardware reset CLR: RSTS clear and WDT reset control bit, program can clear RSTS and reset WDT by writing "1" into this bit The watchdog timer (WDT) is organized as a 4-bit counter designed to prevent the program from unknown errors. If the WDT overflows, the WDT reset function will be performed. RSTS (Bit 7 of WDT_ST) is set by hardware when the WDT overflows and is cleared by hardware reset or writing 1 to bit 7 of WDT_CLR. The interval of WDT to cause reset is about 0.7s at 6MHz external oscillator. Programming one into the bit 7 of WDT_CLR register can reset the contents of the WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The organization of the watchdog timer is shown as below
WDT
Fosc/2^18
Overflow signal
Qw1 Qw2 Qw3 Qw4
R R R R S Q R
System Reset
WDT_ST.7 Hardware reset WDT_CLR.7 <- 8XH
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MPC235 Data Sheet
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System Control Registers
Power saving control
Address
Name
PWR_CTL 0200H Write "0" to Bit 7
Bit 7 0
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 -
Bit 2 -
Bit 1 CKC
Bit 0 HALT
R -
W
When the low-voltage detector is enabled, and it senses the power voltage is lower than VLVR, the chip would be reset automatically. CKC: Oscillator control bit. 1: disable OSC, 0: enable OSC HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line Program can switch the normal operation mode to the power-saving mode for saving power consumption through this register. There are two power saving mode in this system. Stop mode: (PWR_CTL.CKC = 1) System clock stops oscillating. The uC can be awakened from stop mode by 5 ways: port 3 interrupt, hardware reset, power-on reset, USB Host Reset and USB Host Resume. Halt mode: (PWR_CTL.HALT = 1) The FCPU clock in off-line status. The oscillator oscillates or not depends on the content of PWR_CTL.CKC. The uC can be awakened from halt mode by 3-ways: interrupts (USB, Timer 0, Port 3, Port0.4, Port0.5) assigned in the RLH_EN register, hardware reset, or power-on reset.
Release halt mode enable flag
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0202H RLH_EN P05 P04 P3 TM0 USB Program can select interrupt sources to release halt mode through this register. 0: Disable (default) 1: Enable Release halt status flag is the IRQ_ST register. Bit 0 R W
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MPC235 Data Sheet
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FCPU selector
Address Name Bit 7 Bit 6 Bit 5 Bit 4 0201H FCPU_SR CKS: FCPU clock source select. 0: FOSC/2, 1: FOSC Bit 3 Bit 2 Bit 1 Bit 0 CKS R W
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MPC235 Data Sheet
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Timer
Timer 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 00C5H TM0 T7 T6 T5 T4 T3 T2 T1 00C6H TM0_CTL STC RL/S TKI2 TKI1 STC: Timer clock disable/enable. 0: disable timer clock, 1: enable timer clock RL/S: Auto-reload disable/enable. 0: enable auto-reload, 1: disable auto-reload TKI2 0 0 0 0 1 1 1 1 TKI1 0 0 1 1 0 0 1 1 TKI0 0 1 0 1 0 1 0 1 Selected TM0 input clock source FOSC / 8 FOSC / 16 FOSC / 32 FOSC / 64 FOSC / 128 FOSC / 256 FOSC / 512 FOSC / 1024 Bit 0 T0 TKI0 R W
Timer 0 is a dual function 8-bit counter. When timer 0 is under user's firmware control, it will pre-load value to counter at the rising edge of TM0_CTL.STC and its underflow frequency of timer 0 can be calculated with the following equation: FTM0_UV = FTM0CK / (TM0+1) where FTM0CK is selected by TM0_CTL.TKI2/11/10 For example: if FTM0CK= FOSC / 32 (187.5 KHz) TM1 FTM0_UV Frequency 00H invalid 01H 93.75 KHz 02H 62.5 KHz ... ... FFH 732.42 Hz Writing data to the TM0 would write data to the reload buffer of the timer 0. Reading data from the TM0 would read the run-time value from the counter.
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MPC235 Data Sheet
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USB
USB Block Diagram
EP0: Only for Control Transfer EP1EP2: Only Support Interrupt IN EP3: Support Interrupt IN and Interrupt OUT
USB register access control
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W REGC 00E0H USB_CTL UWT URD USB_ADDR 00E1H UA5 UA4 UA3 UA2 UA1 UA0 00E2H USB_DI UDI7 UDI6 UDI5 UDI4 UDI3 UDI2 UDI1 UDI0 - 00E2H USB_DO UDO7 UDO6 UDO5 UDO4 UDO3 UDO2 UDO1 UDO0 USB_CTL: REGC: 3.3V regulator control. 0: disable, 1: enable URD: USB register read, writing 1 into this bit to read USB register (addressed by USB_ADDR) UWT: USB register write, writing 1 into this bit to write USB register (addressed by USB_ADDR) USB_ADDR: USB register address to be accessed USB_DI: Data to be written into USB register (addressed by USB_ADDR) USB_DO: Data read out from USB register (addressed by USB_ADDR)
Address
The USB engine is an independent unit, which is Low-speed USB 1.1 version compliant, with transceiver and 3.3V regulator built-in. The 3.3V regulator can be controlled by user program through the USB_CTL.REGC control bit. The USB engine contains registers of its own, as attached in next page. User can access the USB registers through the access control registers provided here. The sequence to access USB register should be: Write sequence: Write the address of USB register to be accessed into USB_ADDR Write 1 into USB_CTL.UWT Write data into USB_DI Write 0 into USB_CTL.UWT
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MPC235 Data Sheet
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Read sequence: Write the address of USB register to be accessed into USB_ADDR Write 1 into USB_CTL.URD Read data from USB_DO Write 0 into USB_CTL.URD Whenever USB engine finished a transaction, it will generate an interrupt to acknowledge CPU. User can get information about the transaction through the above sequence. When USB engine received a reset event from host, it will reset itself and generate an interrupt. When USB engine received a resume event from host (the device is in suspend mode), it will generate a signal to enable oscillator. If host and the device are both in suspend mode, a falling edge on P3 can wake the device and firmware com trigger a remote wakeup event from usb engine to host.
USB SFR Category - Descriptions Summary
Mnemonic
DCON FADDR FPCON
Mnemonic
FIE
FIFLG IEN1
Mnemonic
EPINDEX EPCON* RXCNT* RXCON* RXDAT* RXSTAT* TXCNT* TXCON* TXDAT* TXSTAT*
USB Device SFRs Device Control Register Function Address Register Function Power Control Register USB Interrupt System SFRs USB Function Interrupt Enable Register USB Function Interrupt Flag Register USB Interrupt Enable Register USB Endpoint SFRs Endpoint Index Register Endpoint Control Register Receive FIFO Byte-Count Register Receive FIFO Control Register Receive FIFO Data Register Endpoint Receive Status Register Transmit FIFO Byte-Count Register Transmit FIFO Control Register Transmit FIFO Data Register Endpoint Transmit Status Register
Address
Description - - - - A6 - - A5 FRWU - A4 - - A3 URST Description - - - FRXIE3 FTXIE2 FTXIE1 FRXIE0 FTXIE0 EP3DIR A2 - PUREN A1 FRSM
CONPUEN
01H 08H 12H
Address
A0 FSUS
18H
1AH 10H
Address
- -
-
- -
FRXD3 -
FTXD2 EFSR
FTXD1 -
FRXD0 EF
FTXD0 -
Description - RXSTL - RXCLR RD7 RXSEQ - TXCLR TD7 TXSEQ - TXSTL - - RD6
RXSETUP
31H 21H 26H 24H 23H 22H 36H 34H 33H 32H
- - - - RD5 STOVW - - TD5 -
- - -
RXFFRC
- - RXBC3 - RD3 RXSOVW TXBC3 - TD3 TXSOVW
-
RXEPEN
EPINX1 - RXBC1 - RD1 - TXBC1 - TD1 -
EPINX0 TXEPEN RXBC0 - RD0 - TXBC0 - TD0 -
RXBC2 - RD2 - TXBC2 - TD2 -
RD4 EDOVW - - TD4 -
- - TD6 -
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MPC235 Data Sheet
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USB SFR Description
DCON: Device Control Register Read/Write Address: 01H Default: 0XXX_0X00 System Reset Bit Bit Mnemonic Function Number Reserved: 7 Write zero to this bit. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Reserved: 3 Write zero to this bit. Endpoint 3 Direction: 2 EP3DIR When this bit is set by FW to enable endpoint 3 to be a TX endpoint. Endpoint 3 behaves as a RX endpoint when this bit is cleared to `0'. D- Pull-Up Resistor Enable: 1 PUREN When this bit is set to `1', enable internal D- pull-up resistor. After setting this bit, the device will act a connection to USB host. Device USP Connection Pull-Up Enable: This bit is used by FW to control whether device is connected to upper host/hub via driving bus SE0. Set `1' to release bus to expose the D0 CONPUEN pull-up resistor. Clear `0' to force bus SE0 to inhibit the D- pull-up resistor. Default is set to `1' after reset. FW can clear to `0' to disable connection to upper host/hub. Note: MPC2F35 do not have EP3DIR, Endpoint 3 is dedicated RX FIFO.
FADDR: USB Function Address Register Read/Write Address: 08H Default: X000_0000 System Reset or USB Reset Bit Bit Function Number Mnemonic Reserved: 7 Write zero to this bit. Function Address: 6:0 A [6:0] This register holds the address for the USB function. During bus enumeration, it is written with a unique value assigned by the host.
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MPC235 Data Sheet
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FPCON: Function Power Control Register Read/Write Address: 12H Default: XX0X_0X00 System Reset or USB Reset Bit Bit Function Number Mnemonic Reserved: 7 Write zero to this bit. Reserved: 6 Write zero to this bit. Function Remote Wake-up Trigger: 5 FRWU This bit is used by the function to initiate a remote wake-up on the USB bus when uC is wake-up by the external trigger. Reserved: 4 Write zero to this bit. USB Reset Flag: Set by hardware when the function detects the USB bus reset. If this bit is 3 URST set, and then the chip will generate the interrupt. Should be cleared by firmware ( write zero ) when serving the USB reset interrupt. Reserved: 2 Write zero to this bit. Function Resume Flag: Set by hardware when the function detects the resume state on the USB 1 FRSM bus. If this bit is set, and then the chip will generate the interrupt. Cleared by firmware ( write zero ) when servicing the function resume interrupt. Function Suspend Flag: Set by hardware when the function detects the suspend state on the USB 0 FSUS bus. If this bit is set, and then the chip will generate the interrupt. During the function suspend ISR, firmware should clear this bit ( write zero ) before enter the suspend mode. FIE: Function Interrupt Enable Register Read/Write Address: 18H Default: XXX0_0000 System Reset or USB Reset Bit Bit Function Number Mnemonic Reserved: 7 Write zero to this bit. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Function Transmit/Receive Interrupt Enable 3: 4 FRXIE3 Enables the transmit/receive done interrupt for function endpoint 3 (FRXD3/FTXD3). Function Transmit Interrupt Enable 2: 3 FTXIE2 Enables the transmit done interrupt for function endpoint 2 (FTXD2). Function Transmit Interrupt Enable 1: 2 FTXIE1 Enables the transmit done interrupt for function endpoint 1 (FTXD1). Function Receive Interrupt Enable 0: 1 FRXIE0 Enables the receive done interrupt for function endpoint 0 (FRXD0). Function Transmit Interrupt Enable 0: 0 FTXIE0 Enables the transmit done interrupt for function endpoint 0 (FTXD0).
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MPC235 Data Sheet
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FIFLG: Function Interrupt Flag Register Read/Write Address: 1AH Default: XXX0_0000 System Reset or USB Reset Bit Bit Function Number Mnemonic Reserved: 7 Write zero to this bit. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Function Transmit/Receive Done Flag 3: 4 FRXD3 For endpoint 3, uC can read/write-clear on this bit. This bit is cleared firmware writes `1' to it. Function Transmit Done Flag 2: 3 FTXD2 For endpoint 2, uC can read/write-clear on this bit. This bit is cleared firmware writes `1' to it. Function Transmit Done Flag 1: 2 FTXD1 For endpoint 1, uC can read/write-clear on this bit. This bit is cleared firmware writes `1' to it. Function Receive Done Flag 0: 1 FRXD0 For endpoint 0, uC can read/write-clear on this bit. This bit is cleared firmware writes `1' to it. Function Transmit Done Flag 0: 0 FTXD0 For endpoint 0, uC can read/write-clear on this bit. This bit is cleared firmware writes `1' to it.
when
when
when
when
when
IEN1: USB Interrupt Enable Register Read/Write Address: 10H Default: XXXX_0X0X System Reset Bit Bit Function Number Mnemonic Reserved: 7 Write "ONE" to this bit. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Enable Function Suspend/Resume: 3 EFSR Function suspend/resume/usb_reset interrupt enable bit. Reserved: 2 Write zero to this bit. Enable Function: 1 EF Transmit/receive done interrupt enable bit for USB function endpoints. Reserved: 0 Write zero to this bit.
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MPC235 Data Sheet
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EPINDEX: Endpoint Index Register Read/Write Default: XXXX_XX00 Bit Bit Function Number Mnemonic Reserved: 7 Write zero to this bit. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Reserved: 3 Write zero to this bit. Reserved: 2 Write zero to this bit. Endpoint Index Bit 1:0: EPINDEX [7:0] = XXXX XX00: Function Endpoint 0 1:0 EPINX1:0 = XXXX XX01: Function Endpoint 1 = XXXX XX10: Function Endpoint 2 = XXXX XX11: Function Endpoint 3
Address: 31H System Reset or USB Reset
EPCON: Endpoint Control Register (Endpoint-Indexed) Read/Write Address: 21H Default: 00XX_X0X0 System Reset or USB Reset Bit Bit Function Number Mnemonic Stall Receive Endpoint: 7 RXSTL Set this bit to stall the receive endpoint. Stall Transmit Endpoint: 6 TXSTL Set this bit to stall the transmit endpoint. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Reserved: 3 Write "ONE" to this bit. Receive Endpoint Enable: 2 RXEPEN Set this bit to enable the receive endpoint. When disabled, the endpoint does not respond to a valid OUT or SETUP token. Reserved: 1 Write "ONE" to this bit. Transmit Endpoint Enable: 0 TXEPEN This bit is used to enable the transmit endpoint. When disabled, the endpoint does not respond to a valid IN token.
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MPC235 Data Sheet
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RXCNT: Receive FIFO Byte-Count Register (Endpoint-Indexed) Read Only Address: 26H Default: XXXX_0000 System Reset or USB Reset Bit Bit Function Number Mnemonic Reserved: 7 Write zero to this bit. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Store receives byte count. Maximum is 8 bytes. 3:0 RXBC[3:0] Receive Byte Count
RXCON: Receive FIFO Control Register (Endpoint-Indexed) Read/Write Address: 24H Default: 0XX0_XXXX System Reset or USB Reset Bit Bit Function Number Mnemonic Receive FIFO Clear: Set this bit to flush the entire receive FIFO. All FIFO statuses are reverted 7 RXCLR to their reset states. Hardware clears this bit when the flush operation is completed. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. FIFO Read Complete: Set this bit (write one) to release the receive FIFO when data set read is 4 RXFFRC complete. Hardware clears this bit after the FIFO release operation has been finished. Reserved: 3 Write zero to this bit. Reserved: 2 Write zero to this bit. Reserved: 1 Write zero to this bit. Reserved: 0 Write zero to this bit.
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MPC235 Data Sheet
23
RXDAT: Receive FIFO Data Register (Endpoint-Indexed) Read Only Address: 23H Default: XXXX_XXXX System Reset or USB Reset Bit Bit Function Number Mnemonic Receive FIFO data specified by EPINDEX is stored and read from this 7:0 RD [7:0] register.
RXSTAT: Endpoint Receive Status Register (Endpoint-Indexed) Read/Write Address: 22H Default: 0000_0XXX System Reset or USB Reset Bit Bit Function Number Mnemonic Receive Endpoint Sequence Bit (read, conditional write): The bit will be toggled on completion of an ACK handshake in response to 7 RXSEQ an OUT token. This bit can be written by firmware if the RXSOVW bit is set when written along with the new RXSEQ value. Received Setup Transaction: 6 RXSETUP This bit is set by hardware when a valid SETUP transaction has been received. Clear this bit by framware to write "0". Start Overwrite Flag (read-only): Set by hardware upon receipt of a SETUP token for any control endpoint to 5 STOVW indicate that the receive FIFO is being overwritten with new SETUP data. This bit is used only for control endpoints. End Overwrite Flag: This flag is set by hardware during the handshake phase of a SETUP 4 EDOVW stage. This bit is cleared by firmware (write zero) after read FIFO data. This bit is only used for control endpoints. Receive Data Sequence Overwrite Bit: Write `1' to this bit to allow the value of the RXSEQ bit to be overwritten. 3 RXSOVW Writing a `0' to this bit has no effect on RXSEQ. This bit always returns `0' when read. Reserved: 2 Write zero to this bit. Reserved: 1 Write zero to this bit. Reserved: 0 Write zero to this bit. Note: When RXSETUP is set by hardware, device will return NAK when receive a IN or OUT Token from USB Host.
24
MPC235 Data Sheet
MEGAWIN
TXCNT: Transmit FIFO Byte-Count Register (Endpoint-Indexed) Write Only Address: 36H Default: XXXX_XXXX System Reset or USB Reset Bit Bit Function Number Mnemonic Reserved: 7 Write zero to this bit. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Store transmits byte count. Maximum is 8 bytes. 3:0 TXBC[3:0] Transmit Byte Count
TXCON: Transmit FIFO Control Register (Endpoint-Indexed) Read/Write Address: 34H Default: 0XXX_XXXX System Reset or USB Reset Bit Bit Function Number Mnemonic Transmit FIFO Clear: Set this bit to flush the entire transmit FIFO. All FIFO statuses are reverted 7 TXCLR to their reset states. Hardware clears this bit when the flush operation is completed. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Reserved: 3 Write zero to this bit. Reserved: 2 Write zero to this bit. Reserved: 1 Write zero to this bit. Reserved: 0 Write zero to this bit. Note: Before write "1" to TXCLR, firmware must write "1" to RXFFRC.
MEGAWIN
MPC235 Data Sheet
25
TXDAT: Transmit FIFO Data Register (Endpoint-Indexed) Write Only Address: 33H Default: XXXX_XXXX System Reset or USB Reset Bit Bit Function Number Mnemonic Data to be transmitted in the FIFO specified by EPINDEX is written to this 7:0 TD [7:0] register.
TXSTAT: Endpoint Transmit Status Register (Endpoint-Indexed) Read/Write Address: 32H Default: 0XXX_0XXX System Reset or USB Reset Bit Bit Function Number Mnemonic Transmit Endpoint Sequence Bit (read, conditional write): The bit will be transmitted in the next PID and toggled on a valid ACK 7 TXSEQ handshake of an IN transaction. This bit can be written by firmware if the TXSOVW bit is set when written along with the new TXSEQ value. Reserved: 6 Write zero to this bit. Reserved: 5 Write zero to this bit. Reserved: 4 Write zero to this bit. Transmit Data Sequence Overwrite Bit: Write a "1" to this bit to allow the value of the TXSEQ bit to be overwritten. 3 TXSOVW Writing a "0" to this bit has no effect on TXSEQ. This bit always returns "0" when read. Reserved: 2 Write zero to this bit. Reserved: 1 Write zero to this bit. Reserved: 0 Write zero to this bit.
26
MPC235 Data Sheet
MEGAWIN
I/O Ports
Port 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R 00D0H P0_BUF BP07 BP06 BP05 BP04 BP03 BP02 BP01 BP00 00D8H P0 P07 P06 P05 P04 P03 P02 P01 P00 0240H P0_CR CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 MP05 MP04 MP01 MP00 0241H P0_MR Port 0 is an 8-bit I/O port; each pin can be programmed as input or output individually. P0_BUF: Port 0 output buffer. When P0.n is configured as an output pin, it outputs the content P0_BUF.n. P0: Port 0 pad value. P0_CR: p0.0~p0.7 is input or output. 0: input, 1: output P0_MR: p0.0~p0.7, pull-high, CMOS/NMOS P0_MR.0: P0.0 ~ P0.3 Pull-high control, 0: disable, 1: enable P0_MR.1: P0.0 ~ P0.3 CMOS/NMOS selector, 0: CMOS, 1:NMOS P0_MR.4: P0.4 ~ P0.7 Pull-high control, 0: disable, 1: enable P0_MR.5: P0.4 ~ P0.7 CMOS/NMOS selector, 0: CMOS, 1:NMOS W of
At initial reset, the port P0 is all in input mode. Each pin of port P0 can be specified as input or output mode independently by the P0_CR registers. When P0 is used as output port, CMOS or NMOS open drain output type can be selected by the P0_MR register. Port P0 has 27kohm internal pull-high resistors that can be enabled/disabled by specifying the P0_MR.0 and P0_MR.4 respectively. The pull-high resistor is automatically disabled only when port is configured as CMOS output. Schmitt trigger circuit is added in the input path of P0.0~P0.3. User should be careful on setting pin as input with no pull high resistor since this setting has potential to cause leakage. When P0.4 and P0.5 are set as input pins, they are interrupt sources. A falling edge at these two pin will set corresponding IRQ_ST bits to 1, and their interrupt subroutines will be executed if corresponding IRQ_EN bits are set.
Port 1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 00D1H P1_BUF BP17 BP16 BP15 BP14 BP13 BP12 00D9H P1 P17 P16 P15 P14 P13 P12 0244H P1_CR CP17 CP16 CP15 CP14 CP13 CP12 MP15 MP14 0245H P1_MR Port 1 is an 8-bit I/O port; refer to port 0 for more information. P1_BUF: Port 1 output buffer. When P1.n is configured as an output pin, it P1_BUF.n. P1: Port 1 pad value. P1_CR: P1.0 ~ P1.7 is input or output. 0: input, 1: output P1_MR: P1.0 ~ P1.7, pull-high and CMOS/NMOS Bit 1 BP11 P11 CP11
MP11
Bit 0 BP10 P10 CP10
MP10
R
W
outputs the content of
MEGAWIN
MPC235 Data Sheet
27
Port 2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 00D2H P2_BUF BP27 BP26 BP25 BP24 BP23 BP22 00DAH P2 P27 P26 P25 P24 P23 P22 0248H P2_CR CP27 CP26 CP25 CP24 CP23 CP22 MP25 MP24 0249H P2_MR Port 2 is an 8-bit I/O port; refer to port 0 for more information. P2_BUF: Port 2 output buffer. When P2.n is configured as an output pin, it P2_BUF.n. P2: Port 2 pad value. P2_CR: P2.0 ~ P2.7 is input or output. 0: input, 1: output P2_MR: P2.0 ~ P2.7, pull-high and CMOS/NMOS Bit 1 BP21 P21 CP21
MP21
Bit 0 BP20 P20 CP20
MP20
R
W
outputs the content of
Port 3
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 00D3H P3_BUF BP37 BP36 BP35 BP34 BP33 BP32 00D9H P3 P37 P36 P35 P34 P33 P32 0244H P3_CR CP37 CP36 CP35 CP34 CP33 CP32 MP35 MP34 0245H P3_MR Port 3 is an 8-bit I/O port; refer to port 0 for more information. P3_BUF: Port 3 output buffer. When P3.n is configured as an output pin, it P3_BUF.n. P3: Port 3 pad value. P3_CR: P3.0 ~ P3.7 is input or output. 0: input, 1: output P3_MR: P3.0 ~ P3.7, pull-high and CMOS/NMOS Bit 1 BP31 P31 CP31
MP31
Bit 0 BP30 P30 CP30
MP30
R
W
outputs the content of
When P3 port is used as input mode, it is an interrupt source, a falling edge at any pin will set the IRQ_ST.P3. The same event can release suspend mode (enable oscillator), and release halt mode (resume Fcpu) if RLH_EN.P3 is set. An interrupt subroutine will be executed if IRQ_EN.P3 is set.
Port 4
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 00D1H P4_BUF BP47 BP46 BP45 BP44 BP43 BP42 00DCH P4 0250H P4_CR 0251H P4_MR Port 4 is a 2-bit I/O port; refer to port 0 for more information. P4_BUF: Port 4 output buffer. When P4.n is configured as an output pin, it P4_BUF.n. P4: Port 4 pad value. P4_CR: P4.0 ~ P4.1 is input or output. 0: input, 1: output P4_MR: P4.0 ~ P4.1, pull-high and CMOS/NMOS Bit 1 BP41 P41 CP41
MP41
Bit 0 BP40 P40 CP40
MP40
R
W
outputs the content of
28
MPC235 Data Sheet
MEGAWIN
Input/Output Pin --- P0~P4
Vdd
P0MR.1
Enable
Output Buffer DATA BUS
Enable
P0CR.x
I/O PIN P0.n
P0MR.0
LDA P0BUF Instruction P0CR.x P0MR.1
Enable
LDA P0 Instruction
DPM control
Address Name Bit 7 Bit 6 Bit 5 00E8H DPM_CTL 00E9H DPMO 00EAH DPMI DPM_CTL: C1, C0: D+/D- control selector. 0x: controlled by USB Engine 10: controlled by CPU Bit 4 Bit 3 Bit 2 Bit 1 C1 DPO DPI Bit 0 C0 DMO DMI R W -
DPMO: DPO/DMO: D+/D- pin output (at {DPM_CTL.C1, DPM_CTL.C0}=10). 0: output low, 1: pull high (input) DPMI: DPI/DMI: D+/D- pin value (Read only) MPC235 provides a way to control D+ and D- pins by user's firmware. The control focuses on PS/2 interface and in system program operations. The DPM.DPI and DPM.DMI record the D+ and D- pin value respectively. For PS/2 interface, firmware can judge the D+ and D- pins' connection be USB or PS/2 protocol by reading the value of DPI and DMI. The DPM_CTL.C1 and DPM_CTL.C0 set the controller of D+ and D- pins. If they are set to 10, the D+ and D- pins are under CPU's control, thus the USB function is unavailable. DPM.DPO/DMO sets the value of D+/D- pin when CPU controls the D+/D- pin; Writing 0 to DPO/DMO let the D+/D- pin to output low, writing 1 causes the pin to be pulled high (input mode). This I/O control would be enough to perform PS/2 operation.
MEGAWIN
MPC235 Data Sheet
29
Programming Notice
The status after different reset condition is listed below: Power on reset CPU RESB pin reset SRAM Data Unknown Unchanged CPU Register Special Function Register *: some SFR are unchanged Unknown Default value Unknown Default value (*) WDT reset Unchanged Unknown Default value (*)
30
MPC235 Data Sheet
MEGAWIN
Application Circuit
Normal:
Note: The capacitor between RESB-pin and ground must be below 0.1uF.
USB keyboard:
MEGAWIN
MPC235 Data Sheet
31
Pad Assignment
MPC235
VSS VSS XTAL1 XTAL2 P04 P05 P40 P41 P06 P07 P10 P11 P12 P13
32
P00 P01 P02 P03 VCC VCC
V33
The substrate should be connected to Vss
DM
DP
LOGO
RESB P37 P36 P35 P34 P33 P32 P31 P30 P27 P21 P20 P17 P16 P15 P14
MPC235 Data Sheet
P26 P25 P24 P23 P22
MEGAWIN
MPC235 Pad Assignment Pad Name X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P00 P01 P02 P03 VDD VDD DP V33 DM VSS VSS XTAL1 XTAL2 P04 P05 P40 P41 P06 P07 P10 P11 P12 1177.4 1047.4 937.4 827.4 717.4 607.4 344 -110.7 -565.4 -828.8 -938.8 -1048.8 -1178.8 -1178.8 -1178.8 -1178.8 -1178.8 -1178.8 -1178.8 -1178.8 -1178.8 -1178.8
Y 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 1167.9 96.3 -13.7 -123.9 -233.9 -362.95 -491.1 -601.3 -711.3 -821.5
Pad 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Name P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 RESB
X -1178.8 -961.4 -851.4 -741.2 -631.2 -521 -411 489.45 599.45 709.65 819.65 929.85 1177.4 1177.4 1177.4 1177.4 1177.4 1177.4 1177.4 1177.4 1177.4 1177.4
Y -931.5 -1170.8 -1170.8 -1170.8 -1170.8 -1170.8 -1170.8 -1170.8 -1170.8 -1170.8 -1170.8 -1170.8 -970.65 -860.65 -750.45 -640.45 -530.25 -420.25 -310.05 -200.05 -89.85 22.75
MEGAWIN
MPC235 Data Sheet
33
Absolute Maximum Rating
Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VCC with respect to Ground Maximum total current through VCC and Ground Maximum output current sunk by any Port pin Rating -55 ~ +125 -65 ~ + 150 -0.5 ~ VCC + 0.5 -0.5 ~ +6.0 100 25 Unit C C V V mA mA
*Note: stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
34
MPC235 Data Sheet
MEGAWIN
DC Characteristics
(VDD-VSS = 5.0 V, FOSC = 6MHz, Ta = 25 C; unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. Op. Voltage VDD 4.35 Op. Current Suspend Current Input High Voltage Input Low Voltage Port 0, 1, 2, 3 drive current Port 0.4~0.7, 1, 2, 3 sink current Port 0.0~0.3 sink current Internal Pull-high Resistor Low Voltage Reset IOP ISUS VIH VIL IOH IOL1 IOL2 RPH VLVR No load (Ext.-V) In normal operation No load (Ext.-V) VOH = 4.5V, VDD = 5.0V VOL = 0.4V, VDD = 5.0V VOL = 3.2V, VDD = 5.0V VIL = 0V 2 0 6 TYP. 300 2.5 4.0 8 27K 3.6 MAX. 5.5 20 450 VDD 0.8 V UNIT V mA A V V mA mA mA
MEGAWIN
MPC235 Data Sheet
35
AC Characteristics
PARAMETER CPU Op. Frequency POR duration SYM. FCPU TPOR CONDITIONS VDD = 5.0V FOSC = 6 MHz MIN. 0.5 10 TYP. 3 MAX. UNIT MHz mS
36
MPC235 Data Sheet
MEGAWIN
Instruction Set Summary
Addressing Mode Table
Address Mode 1 Absolute a 2 Absolute Indexed Indirect (a,x) 3 Absolute Indexed with X a,x 4 Absolute Indexed with Y a,y 5 Absolute Indirect (a) 6 Accumulator A 7 Immediate # 8 Implied i 9 Program Counter Relative r 10 Stack s 11 Zero Page zp 12 Zero Page Indexed Indirect (zp,x) 13 Zero Page Indexed with X zp,x 14 Zero Page Indexed with Y zp,y 15 Zero Page Indirect (zp) 16 Zero Page Indirect Indexed with Y (zp),y Instruction Times in Memory Cycle 4(3) 5 4(1,3) 4(1) 4(3) 2 2 2 2(2) 3-7 3(3) 6 4(3) 4 5 5 Memory Utilization in Number of Program Sequence Bytes 3 3 3 3 3 1 2 1 2 1-4 2 2 2 2 2 2
Notes: (indicated in parenthesis) 1. Page boundary, add 1 cycle if page boundary is crossed when forming address 2. Branch taken, add 1 cycle if branch is taken 3. Read-Modify-Write, add 2 cycles
MEGAWIN
MPC235 Data Sheet
37
Instruction Set Table
ADC Add memory to accumulator with Carry AND "AND" memory with accumulator ASL BBR BBS BCC BCS BEQ BIT BMI BNE BPL BRA BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP JSR LDA LDX LDY LSR Load the Y register with memory Logical Shift one bit Right memory or accumulator
Arithmetic Shift one bit Left, memory or NOP No Operation accumulator Branch on Bit Reset ORA "OR" memory with Accumulator Branch of Bit Set PHA Push Accumulator on stack Branch on Carry Clear (Pc=0) PHP Push Processor status on stack Branch on Carry Set (Pc=1) PHX Push X register on stack Branch if Equal (Pz=1) PHY Push Y register on stack Bit Test PLA Pull Accumulator from stack Branch if result Minus (Pn=1) PLP Pull Processor status from stack Branch if Not Equal (Pz=0) PLX Pull X register from stack Branch if result Plus (Pn=0) PLY Pull Y register from stack Branch Always RMB Reset Memory Bit Rotate one bit Left memory or Branch on overflow Clear (Pv=0) ROL accumulator Rotate one bit Right memory or Branch on overflow Set (Pv=1) ROR accumulator Clear Cary flag RTI Return from Interrupt Clear Decimal mode RTS Return from Subroutine Subtract memory from accumulator with Clear Interrupt disable bit SBC borrow (Carry bit) Clear overflow flag SED Set Decimal mode Compare memory and accumulator SEI Set Interrupt disable status Compare memory and X register SMB Set Memory Bit Compare memory and Y register STA Store Accumulator in memory Decrement memory or accumulate by STX Store the X register in memory one Decrement X by one STY Store the Y register in memory Decrement Y by one STZ Store Zero in memory "Exclusive OR" memory with accumulate TAX Transfer the Accumulator to the X register Increment memory or accumulate by one TAY Transfer the Accumulator to the Y register Increment X register by one TRB Test and Reset memory Bit Increment Y register by one TSB Test and Set memory Bit Transfer the Stack pointer to the X Jump to new location TSX register Jump to new location Saving Return TXA Transfer the X register to the Accumulator (Jump to Subroutine) Transfer the X register to the Stack Load Accumulator with memory TXS pointer register Load the X register with memory TYA Transfer Y register to the Accumulator
38
MPC235 Data Sheet
MEGAWIN
MSD 2
TSB zp 5,2 TRB zp ORA zp,x ASL zp,x RMB1 zp CLC i ORA a,y INC A 5,2 BIT zp 3,2 BIT zp,x AND zp,x ROL zp,x RMB3 zp SEC i AND a,y DEC A 4,2 EOR zp 3,2 EOR zp,x LSR zp,x RMB5 zp CLI i EOR a,y PHY s 4,2 STZ zp 3,2 STZ zp,x ADC zp,x ROR zp,x RMB7 zp SEI i ADC a,y PLY s 4,2 STY zp 3,2 3,2 3,2 5,2 2,1 2,2 STA zp STX zp SMB0zp DEY i BIT # 4,2 6,2 5,2 2,1 4,3 4,1 TXA i 2,1 3,2 5,2 5,2 4,1 2,2 2,1 ADC zp ROR zp RMB6 zp PLA s ADC # ROR A 6,2 5,2 2,1 4,3 3,1 JMP (a) 6,3 5,2 5,2 3,1 2,2 2,1 3,3 4,3 LSR zp RMB4 zp PHA s EOR # LSR A JMP a EOR a 4,2 6,2 5,2 2,1 4,3 2,1 4,3 4,3 6,3 BIT a,x 3,2 5,2 5,2 4,1 2,2 2,1 4,3 4,3 6,3 AND zp ROL zp RMB2 zp PLP s AND # ROL A BIT a AND a ROL a BBR2 r 5,3 4,2 6,2 5,2 2,1 4,3 2,1 6,3 4,3 6,3 5,3 TRB a ORA a,x ASL a,x BBR1 r 3,2 5,2 5,2 3,1 2,2 2,1 6,3 4,3 6,3 5,3 ORA zp ASL zp RMB0 zp PHP s ORA # ASL A TSB a ORA a ASL a BBR0 r
MSD 3 0 1 2 3
5,3 LSR a BBR4 r 6,3 5,3
0
1
4
5
6
7
8
9
A
B
C
D
E
F
0
ORA (zp,x)
6,2
1
5,2
BPL r ORA (zp),y ORA (zp)
2,2
5,2
Instruction Set Summary
MEGAWIN
AND a,x ROL a,x BBR3 r 5,2
2
JSR a AND (zp,x)
6,3
6,2
3
BMI r AND (zp),y AND (zp)
2,2
5,2
4
RTI s EOR (zp,x)
4 5
6,1
6,2
5
5,2
BVC r EOR (zp),y EOR (zp)
EOR a,x LSR a,x BBR5 r 4,3 ADC a 4,3 6,3 5,3 ROR a BBR6 r 6,3 5,3 JMP (a,x) ADC a,x ROR a,x BBR7 r 6,3 STY a 4,3 STZ a 4,3 STA a 4,3 6,3 5,3 STX a BBS0 r 4,3 5,3 STA a,x STZ a,x BBS1 r
2,2
5,2
6
RTS s ADC (zp,x)
6 7 8 9
6,1
6,2
7
5,2
BVS r ADC (zp),y ADC (zp)
2,2
5,2
MPC235 Data Sheet
STY zp,x STA zp,x STX zp,y SMB1 zp TYA i STA a,y TXS i 4,2 LDY zp 3,2 3,2 3,2 5,2 LDA zp LDX zp 4,2 4,2 5,2 2,1 4,3 LDA # 2,1 2,2 2,1 TAX i 2,1 5,2 LDX # 2,2 SMB2 zp TAY i LDY zp,x LDA zp,x LDX zp,y SMB3 zp CLV i LDA a,y TSX i 4,2 CPY zp 3,2 3,2 CMP zp 4,2 4,2 5,2 2,1 4,3 CMP # 5,2 5,2 2,1 2,2 2,1 DEX i 2,1 5,2 DEC zp SMB4 zp INY i CMP zp,x DEC zp,x SMB5 zp CLD i CMP a,y PHX s 4,2 CPX zp 3,2 SBC zp 3,2 6,2 INC zp 5,2 5,2 2,1 SMB6 zp INX i 5,2 2,1 4,3 SBC # 2,2 3,1 NOP i 2,1 SBC zp,x INC zp,x SMB7 zp SED i SBC a,y PLX s 4,2 6,2 5,2 2,1 4,3 4,1 5,2 5,2
8
BRA r STA (zp,x)
3,2
6,2
9
BCC r STA (zp),y STA (zp)
2,2
6,2
4,3 LDY a 4,3
4,3 LDA a 4,3
5,3
5,3 LDX a BBS2 r 4,3 5,3 LDY a,x LDA a,x LDX a,y BBS3 r 4,3 CPY a 4,3 4,3 CMP a 4,3 4,3 5,3 DEC a BBS4 r 6,3 5,3 CMP a,x DEC a,x BBS5 r 4,3 CPX a 4,3 SBC a 4,3 6,3 INC a 6,3 5,3 BBS6 r 5,3 SBC a,x INC a,x BBS7 r 4,3 6,3 5,3
A
LDY # LDA (zp,x)
A B C D E F
2,2
6,2
B
BCS r LDA (zp),y LDA (zp)
2,2
5,2
C
CPY # CMP (zp,x)
2,2
6,2
D
BNE r CMP (zp),y CMP (zp)
39 2 3 4
2,2
5,2
E
CPX # SBC (zp,x)
2,2
6,2
F
BEQ r SBC (zp),y SBC (zp)
2,2
5,2
0
1
5
6
7
8
9
A
B
C
D
E
F
A: Accumulator X: Index Register X Y: Index Register Y zp: Address8 or zero page a: Adress16 s: Stack r: Relative i : Implied
40
MPC235 Data Sheet
MEGAWIN
Symbol Description
ACC: (ACC): ACC.n: X: Y: SP: PC: #data: C: Z: I: B: D: V: S: addr16: addr8: addr+(index): addr 16: label: ~: : : : : Accumulator Contents of Accumulator Accumulator bit n Index Register X Index Register Y Stack Pointer Register Program Counter Constant parameter Carry Flag Zero Flag Interrupt Disable Status Break Status Decimal Mode Status Overflow Flag Sign Flag Absolute Address Zero Page/Relative Address Combined Address Address Extend to Absolute Address (Get two addr8 contents continuously) Address Variable 1's compliment AND OR Exclusive OR Transfer direction, result
MEGAWIN
MPC235 Data Sheet
41
Arithmetic Operations
Mnemonic ADC Operand(s) #data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y Operation description (ACC) (ACC) + #data + (C) (ACC) (ACC) + (addr8) + (C) (ACC) (ACC) + [(addr8)] + (C) (ACC) (ACC) + [addr8 + (X)] + (C) (ACC) (ACC) + {[addr8 + (X) 16]} + (C) (ACC) (ACC) + [(addr816) + (Y)] + (C) (ACC) (ACC) + (addr16) + (C) (ACC) (ACC) + [addr16 + (X)] + (C) (ACC) (ACC) + [addr16 + (Y)] + (C) (ACC) (ACC) - #data - (~C) (ACC) (ACC) - (addr8) - (~C) (ACC) (ACC) - [(addr8)] - (~C) (ACC) (ACC) - [addr8 + (X)] - (~C) (ACC) (ACC) - {[addr8 + (X) 16]} - (~C) (ACC) (ACC) - [(addr816) + (Y)] - (~C) (ACC) (ACC) - (addr16) - (~C) (ACC) (ACC) - [addr16 + (X)] - (~C) (ACC) (ACC) - [addr16 + (Y)] - (~C) (ACC) (ACC) + 1 (addr8) (addr8) + 1 [addr8 + (X)] [addr8 + (X)] + 1 (addr16) (addr16) + 1 [addr16 + (X)] [addr16 + (X)] + 1 (X) (X) + 1 (Y) (Y) + 1 A addr8 addr8, X (ACC) (ACC) - 1 (addr8) (addr8) - 1 [addr8 + (X)] [addr8 + (X)] - 1 Flag Byte Cycle C, Z, V, 2 2(4) S C, Z, V, 2 3 S C, Z, V, 2 5 S C, Z, V, 2 4 S C, Z, V, 2 6 S C, Z, V, 2 5(1)(4) S C, Z, V, 3 4(4) S C, Z, V, 3 4(1)(4) S C, Z, V, 3 4(1)(4) S C, Z, V, S C, Z, V, S C, Z, V, S C, Z, V, S C, Z, V, S C, Z, V, S C, Z, V, S C, Z, V, S C, Z, V, S C, Z Z, S Z, S Z, S Z, S Z, S Z, S C, Z Z, S Z, S 2 2 2 2 2 2 3 3 3 1 2 2 3 3 1 1 1 2 2 2(4) 3 5 4 6 5(1)(4) 4(4) 4(1)(4) 4(1)(4) 2 5 6 6 6(1) 2 2 2 5 6
SBC
#data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y
INC
A addr8 addr8, X addr16 addr16, X
INX INY DEC
42
MPC235 Data Sheet
MEGAWIN
addr16 addr16, X DEX DEY CMP #data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y #data addr8 addr16 #data addr8 addr16
(addr16) (addr16) - 1 [addr16 + (X)] [addr16 + (X)] - 1 (X) (X) - 1 (Y) (Y) - 1 (ACC) - #data (ACC) - (addr8) (ACC) - [(addr8)] (ACC) - [addr8 + (X)] (ACC) - {[addr8 + (X) 16]} (ACC) - [(addr816) + (Y)] (ACC) - (addr16) (ACC) - [addr16 + (X)] (ACC) - [addr16 + (Y)] (X) - #data (X) - (addr8) (X) - (addr16) (Y) - #data (Y) - (addr8) (Y) - (addr16)
Z, S Z, S Z, S Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S
3 3 1 1 2 2 2 2 2 2 3 3 3 2 2 3 2 2 3
6 6(1) 2 2 2(4) 3 5 4 6 5(1)(4) 4(4) 4(1)(4) 4(1)(4) 2(4) 3 4(4) 2(4) 3 4(4)
CPX
CPY
Note: * Add one clock period of page boundary is crossed.
MEGAWIN
MPC235 Data Sheet
43
Logic Operations
Mnemonic Operand(s) AND #data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y ORA #data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y #data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y A addr8 addr8, X addr16 addr16, X ROR Operation description (ACC) (ACC) #data (ACC) (ACC) (addr8) (ACC) (ACC) [(addr8)] (ACC) (ACC) [addr8 + (X)] (ACC) (ACC) {[addr8 + (X) 16]} (ACC) (ACC) [(addr816) + (Y)] (ACC) (ACC) (addr16) (ACC) (ACC) [addr16 + (X)] (ACC) (ACC) [addr16 + (Y)] (ACC) (ACC) #data (ACC) (ACC) (addr8) (ACC) (ACC) [(addr8)] (ACC) (ACC) [addr8 + (X)] (ACC) (ACC) {[addr8 + (X) 16]} (ACC) (ACC) [(addr816) + (Y)] (ACC) (ACC) (addr16) (ACC) (ACC) [addr16 + (X)] (ACC) (ACC) [addr16 + (Y)] (ACC) (ACC) #data (ACC) (ACC) (addr8) (ACC) (ACC) [(addr8)] (ACC) (ACC) [addr8 + (X)] (ACC) (ACC) {[addr8 + (X) 16]} (ACC) (ACC) [(addr816) + (Y)] (ACC) (ACC) (addr16) (ACC) (ACC) [addr16 + (X)] (ACC) (ACC) [addr16 + (Y)] (C) (ACC.7), (ACC.(n+1)) (ACC. n), (ACC.0 ) (C) (C) (addr8.7), (addr8.(n+1)) (addr8.n), (addr8.0 ) (C) (C) [addr8 + (X).7], [addr8 + (X).(n+1)] [addr8 + (X).n], [addr8 + (X).0] (C) (C) (addr16.7), (addr16.(n+1) ) (addr16.n), (addr16.0 ) (C) (C) [addr16 + (X).7], [addr16 + (X).(n+1)] [addr16 + (X).n], [addr16 + (X).0] (C) (ACC.7 ) (C), (ACC. n) (ACC.(n+1) ), (C) (ACC.0) (addr8.7 ) (C), (addr8. n) (addr8.(n+1) ), (C) (addr8.0) [addr8 + (X).7] (C), [addr8 + (X).n] [addr8 + (X).(n+1)], (C) [addr8 + (X).0] (addr16.7 ) (C), (addr16. n) Flag Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S Byte 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 3 3 3 1 2 2 3 3 Cycle 2(4) 3 5 4 6 5(1)(4) 4(4) 4(1)(4) 4(1)(4) 2(4) 3 5 4 6 5(1)(4) 4(4) 4(1)(4) 4(1)(4) 2(4) 3 5 4 6 5(1)(4) 4(4) 4(1)(4) 4(1)(4) 2 5 6 6 6(1)
EOR
ROL
A addr8 addr8, X addr16
C, Z, S C, Z, S C, Z, S C, Z, S
1 2 2 3
2 5 6 6
44
MPC235 Data Sheet
MEGAWIN
addr16, X ASL
(addr16.(n+1) ), (C) (addr16.0) [addr16 + (X).7] (C), [addr16 + (X).n] C, Z, S [addr16 + (X).(n+1)], (C) [addr16 + (X).0] (C) (ACC.7), (ACC.(n+1) ) (ACC. n), (ACC.0) 0 (C) (addr8.7), (addr8.(n+1) ) (addr8. n), (addr8.0) 0 (C) [addr8 + (X).7], [addr8 + (X).(n+1)] [addr8 + (X).n], [addr8 + (X).0] 0 (C) (ACC.7), (ACC.(n+1) ) (ACC. n), (ACC.0) 0 (C) [addr16 + (X).7], [addr16 + (X).(n+1)] [addr16 + (X).n], [addr16 + (X).0] 0 (ACC.7 ) 0, (ACC. n) (ACC.(n+1) ), (C) (ACC.0) (addr8.7 ) 0, (addr8. n) (addr8.(n+1) ), (C) (addr8.0) [addr8 + (X).7] 0, [addr8 + (X).n] [addr8 + (X).(n+1)], (C) [addr8 + (X).0] (addr16.7 ) 0, (addr16. n) (addr16.(n+1) ), (C) (addr16.0) [addr16 + (X).7] 0, [addr16 + (X).n] [addr16 + (X).(n+1)], (C) [addr16 + (X).0] (ACC) #data (ACC) (addr8) (ACC) [addr8 + (X)] (ACC) (addr16) (ACC) [addr16 + (X)] (addr8) (~ACC) (addr8) (addr16) (~ACC) (addr16) (addr8) (ACC) (addr8) (addr16) (ACC) (addr16) C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S
3
6(1)
A addr8 addr8, X addr16 addr16, X
1 2 2 3 3
2 5 6 6 6(1)
LSR
A addr8 addr8, X addr16 addr16, X
C, Z, S C, Z, S C, Z, S C, Z, S
1 2 2 3
2 5 6 6
C, Z, S
3
6(1)
BIT
#data addr8 addr8, X addr16 addr16, X addr8 addr16 addr8 addr16
Z Z Z Z Z -
2 2 2 3 3 2 3 2 3
2(4) 3 4 4 4(1)(4) 5 6 5 6
TRB
TSB
Note: * Add one clock period of page boundary is crossed.
MEGAWIN
MPC235 Data Sheet
45
Data Transfer
Mnemonic Operand(s) LDA #data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y LDX #data addr8 addr8, Y addr16 addr16, Y #data addr8 addr8, X addr16 addr16, X addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y addr8 addr8, Y addr16 addr8 addr8, X addr16 addr8 addr8, X addr16 addr16, X Operation description (ACC) #data (ACC) (addr8) (ACC) [(addr8)] (ACC) [addr8 + (X)] (ACC) {[addr8 + (X) 16]} (ACC) [(addr816) + (Y)] (ACC) (addr16) (ACC) [addr16 + (X)] (ACC) [addr16 + (Y)] (X) #data (X) (addr8) (X) [addr8 + (Y)] (X) (addr16) (X) [addr16 + (Y)] (Y) #data (Y) (addr8) (Y) [addr8 + (X)] (Y) (addr16) (Y) [addr16 + (X)] (addr8) (ACC) [(addr8)] (ACC) [addr8 + (X)] (ACC) {[addr8 + (X) 16]} (ACC) [(addr816) + (Y)] (ACC) (addr16) (ACC) [addr16 + (X)] (ACC) [addr16 + (Y)] (ACC) (addr8) (X) [addr8 + (Y)] (X) (addr16) (X) (addr8) (Y) [addr8 + (X)] (Y) (addr16) (Y) (addr8) 00H [addr8 + (X)] 00H (addr16) 00H [addr16 + (X)] 00H (X) (ACC) (ACC) (X) (Y) (ACC) (ACC) (Y) Flag Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Byte 2 2 2 2 2 2 3 3 3 2 2 2 3 3 2 2 2 3 3 2 2 2 2 2 3 3 3 2 2 3 2 2 3 2 2 3 3 1 1 1 1 Cycle 2(4) 3 5 4 6 6(1)(4) 4(4) 4(1)(4) 4(1)(4) 2(4) 3 4 4(4) 4(1)(4) 2(4) 3 4 4(4) 4(1)(4) 3 5 4 6 6(1)(4) 4(4) 4(1)(4) 4(1)(4) 3 4 4(4) 3 4 4(4) 3 4 4(4) 5(1)(4) 2 2 2 2
LDY
STA
STX
STY
STZ
TAX TXA TAY TYA
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MPC235 Data Sheet
MEGAWIN
TSX TXS PHA PHP PHX PHY PLA PLP PLX PLY
(X) (SP) (SP) (X) [(SP)] (ACC), (SP) (SP) - 1 [(SP)] (P), (SP) (SP) - 1 [(SP)] (X), (SP) (SP) - 1 [(SP)] (Y), (SP) (SP) - 1 (ACC) [(SP+1)], (SP) (SP) + 1 (P) [(SP+1)], (SP) (SP) + 1 (X) [(SP+1)], (SP) (SP) + 1 (Y) [(SP+1)], (SP) (SP) + 1
Z, S Z, S C, Z, I, D, V, S Z, S Z, S
1 1 1 1 1 1 1 1 1 1
2 2 3 3 3 3 4 4 4 4
Note: * Add one clock period of page boundary is crossed.
Boolean Variable Manipulation
Mnemonic CLC CLI CLD CLV SEC SEI SED SMB0 ... SMB7 RMB0 ... RMB7 addr8 addr8 addr8 addr8 Operand(s) (C) 0 (I) 0 (D) 0 (V) 0 (C) 1 (I) 1 (D) 1 (addr8.0) 1 (addr8.7) 1 (addr8.0) 0 (addr8.7) 0 Operation description Flag C I D V C I D Z Z Z Z Byte Cycle 1 2 1 2 1 2 1 2 1 1 1 2 2 2 2 2 2 2 5 5 5 5
Note: If the assembler does not support this instruction, please use DB to implement it. The OP code of RMB0 ~ RMB7 is 07 ~ 77, and the SMB0 ~ SMB7 is 87 ~ F7.
MEGAWIN
MPC235 Data Sheet
47
Program and Machine Control
Mnemonic Operand(s) JMP addr16 (addr16) (addr16, X) BRA BEQ BNE BCS BCC BMI BPL BVS BVC BBR0 ... BBR7 BBS0 ... BBS7 JSR RTS RTI NOP addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8 label Operation description (PC) label; the label may be address or variable. (PC) (label) (PC) {[label + (X) 16]} (PC) (PC)+addr8 (PC) (PC)+addr8 if Z == 1 (+/- relative) (PC) (PC)+addr8 if Z == 0 (+/- relative) (PC) (PC)+addr8 if C == 1 (+/- relative) (PC) (PC)+addr8 if C == 0 (+/- relative) (PC) (PC)+addr8 if (S == 1) (+/- relative) (PC) (PC)+addr8 if (S == 0) (+/- relative) (PC) (PC)+addr8 if (V == 1) (+/- relative) (PC) (PC)+addr8 if (V == 0) (+/- relative) (PC) (PC)+addr8 if ACC.0 == 0 (+/- relative) (PC) (PC)+addr8 if ACC.7 == 0 (+/- relative) (PC) (PC)+addr8 if ACC.0 == 1 (+/- relative) (PC) (PC)+addr8 if ACC.7 == 1 (+/- relative) stack (PC), (PC) label (PC) pop stack (PC) pop stack, restore status register P No operation Flag C, Z, I, D, V, S Byte Cycle 3 3 3 3 2 2 2 2 2 2 2 2 2 3 3 3 3 3 1 1 6 6(1) 3(2) 2(2)(3) 2(2)(3) 2(2)(3) 2(2)(3) 2(2)(3) 2(2)(3) 2(2)(3) 2(2)(3) 5(2)(3) 5(2)(3) 5(2)(3) 5(2)(3) 6 6 6
1
2
Note: (1) Add 1 cycle for indexing across page boundaries, or write. This cycle contains invalid addresses. Note: (2) Add 1 cycle if branch is taken. Note: (3) Add 1 cycle if branch is taken across page boundaries. Note: (4) Add 1 cycle for decimal mode. Note: If the assembler does not support this instruction, please use DB to implement it. The OP code of BBR0 ~ BBR7 is 0F ~ 7F, and the BBS0 ~ BBS7 is 8F ~ FF.
48
MPC235 Data Sheet
MEGAWIN
Package Dimensions
40-pin DIP
28-SSOP
MEGAWIN
MPC235 Data Sheet
49
Revision History
Version 0.1 1.0 1.1 A2 Date 2003/9 2004/8 2005/1 2005/7 Page Initial document 1,44 41 19~34 Revised the operating voltage from 4.35V to 5.5V Application circuit has been modified. Revised USB SFR Description. Added Memory Map diagram Modify 17k ohm to 27k ohm Revised Pad Define. A3 2008/6 7 Added 6502 instruction Modify Block Diagram Added USB Block Diagram Modify Power Saving Control SFR A4 2008/12 Formatting Description
50
MPC235 Data Sheet
MEGAWIN

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